IEEE Std 802.3cb-2018 pdf free download – IEEE Standard for Ethernet Amendment 1: . Physical Layer Specifications and Management Parameters for 2.5 Gb/s and 5 Gb/s Operation over Backplane
Insent the following nrew subeclauses (45.2 1.18.a and 45.2.1 18b) after the introductory text of 45.2.1.18 te, before 45.2. 1.181):
45.1.18.a 5GBASE-KR ability (1.21.3)
When read as a one, bit 1.21.3 indicates that the PMAPMD is able to operate a a SGBASE KR PMAPMD type. When read as a zero, bit 1.21 3 indicates that the PMA/PMD is not able to operate as a SGBASE-KR PMAPMD type.
45.2.1.18.b 2.5GBASE-KX ability (1.21.2)
When read as a one, bit 1.21.2 indicates that the PMAPMD is able to operate as a 2.5GBASE-KX PMA/PMD type. When read as a zero, bit 1.212 indicates that the PMAPMD is not able to operite as a 2.SGBASE-KX PMA/PMD type.
45.2.1.89 BASE-R PMD control register (Register 1.150)
Insert the fllowing new pangraph ufter the firs pargraph of 45.21.89:
The BASE-R PMD control register is also used by SGBASEKR described in Clause 130 to disable the transmitter equalizer for test purposes. 5GBASE-KR does not use the start-up protocol.
Insert the following new subelause (45.2. 1.89.3) afier 45.2.1.89.2:
45.2.1.89.3 Transmitter equalizer disable (1.150.2)
When bit 1.150.2 is set to one, 5GBASE-KR transmitter equalization is disabled. The default value of bit 1.150.2 is zero.
Change the title and text of 45.2.1.97 as shown:
45.2.1.97 1000BASE-KX/2.5GBASE-KX control register (Register 1.160)
The assignment of bits in the 1000BASE-KX2.5GBASE-KX control register is shown in Table 45-77.
Change the title of Table 45-77 as shown:
Table 45- 77- -1000BASE-KX/2.5GBASE.KX control register
45.2.1.97.1 PMD transmit disable (1.160.0)
Change 45.2.1.97.1 as shown:
This bit disables the 1000BASE-KX transmitter as defined in 70.6.5, or the 2.5GBASE-KX transmitter a defined in 128.6.5.
Change the title and texr of 45.2.1.98 as shown:
45.2.1.98 1000BASE-KX/2.5GBASE-KX status register (Register 1.161)
The assignment of bits in the 1000BASE-KX/2.5GBASE-KX status register is shown in Table 45- -78.
Change the title of Table 45- -78 as shown:
Table 45- 78- 1000BASE-KX/2.5GBASE-KX status register
Change the title and text of 45.2.1.98.6 as shown:
45.2.1.98.6 1000BASE-KX/2.5GBASE-KX signal detect (1.161.0)
The PMD signal detect function is optionat for both 1000BASE-KX PMD (see 70.6.4) and 2.5GBASE-KXPMD (see 128.6.4) is mandatory if EEE is implemented and optional otherwise. The 1 000BASE-X PCS and 2.5GBASE-X PCS requires signal detect to be one before synchronization can occur. If the signal detect function is not implemented, this bit is set to one.
45.2.1.140 Test-pattern ability (Register 1. 1500)
Change the first paragraph of 45.2.1.140 as shown:
The test-pattem ability register is used for PHY types that implement SSPRQ, square wave, and PRBS testing in the PMA. These functions are described in 127.3.4.1. _83.5.10, and 120.5.11. The assignment of bits in the test-patterm ability register is shown in Table 45-105.
45.2.3 PCS registers
Change the indicated rows of Table 45- -176 as shown (unchanged rows not shown):
45.2.3.1 PCS control 1 register (Register 3.0)
45.2.3.1.2 Loopback (3.0.14)
Change the first paragraph of 45.23.1.2 as shown:
When the 100BASE-T1, any MultiGBASE-T, or the 5/10GBASE-R mode of operation is selected for the PCS using the PCS type selction field (3.7.3:0), the PCS shall be placed in a loopback mode of operation when bit 3.0.14 is set to a one. When bit 3.0.14 is set to a one, the 100BASE-T1, 5/10GBASE-R, or any PCS in the MultiGBASE-T set shall accept data on the transmit path and returm it on the receive path. The speed of the loopback is selected by the PCS control 1 (Register 3.0) defined in 45.23.1. The specific behavior of the 100BASE-TI PCS during loopback is specified in 96.3.5. The specific behavior of the 5/10GBASE-R PCS during loopback is specifed in 49.2. The specific behavior for the 10GBASE-T PCS during loopback is specifed in 55.3.7.3. The specific behavior for the 25GBASE-T and 40GBASE-T PCS during loopback is specifed in 113.3.7.3. The specific bchavior for the 2.5GBASE-T or 5GBASE-T PCS during loopback is specifled in 126.3.7.3. For all other port types, the PCS loopback functionality is not applicable and writes to this bit shall be ignored and reads from this bit shall retum a value of zero.IEEE Std 802.3cb pdf download.