IEEE Std 400.4-2015 pdf free download – IEEE Guide for Field Testing of Shielded Power Cable Systems Rated 5 kV and Above with Damped Alternating Current (DAC) Voltage.
6. DAC test circuit and parameters
6.1 Overview To generate DAC voltages, different types of test circuits can be applied [B5], [B9], [B16], [B21], [B29], [B30], [B51], [B73], [B78], [B86]. In this document, the basic circuit shown in Figure 5 will be used to explain the principles of DAC voltage generation. The DAC test circuit basically consists of a HV voltage source generating an increasing unipolar voltage (See Figure 2,) a HV inductor in the range of several [H], a capacitive test object and a suitable HV switch (See Figure 5.) The capacitive test object can consist of one or more capacitive test objects, such as power cables or generators. Even though a cable has distributed parameters, for simplification a lumped capacitor model is used. When the unipolar charging voltage has reached the maximum value VT the HV switch is closed, generating a damped alternating voltage on the capacitive test object. The damping factor depends on the loss characteristics of the test circuit and the test object. The DAC natural frequency ( r f ) is determined by the values of the HV inductor and the capacitance of the test object. Below a certain capacitance value of the test object, the natural frequency of the oscillation will exceed acceptable values. For these cases an additional HV storage capacitor can be connected in parallel to the circuit.
6.2 DAC test voltage circuit
6.2.1 Overview
Basic principles of DAC test circuits are shown in Figure 5 and in 6.3 the parameters relevant for characterizing a DAC test circuit are defined. The complete process of a DAC excitation generation consists of three phases (See also Figure 2)
6.2.1.1 Charging phase
During this phase the test object is stressed with increasing unipolar (negative or positive) voltage. The charging time depends on the maximum available load current of the voltage supply, the test voltage, and the capacitance of the test object. According to Kreuger, 1995 [B53], no dc stresses and steady-state condition occur in the cable under test if the voltage is continuously increasing up till the time of triggering the HV switch.
As a result, space charges are less likely to form in the cable insulation unless the frequency is less than 0.01 Hz and the electric stress is more than 10 kV/mm [B80]. Referring to Dissado, et al. [B13] and Takada [B80], the amount of space charge trapped is a function of frequency and occurs below 0.01 Hz for an applied electric field [B47]. For example, in contrast when applying pure HVDC stress compared to DAC to insulation and according to Kreuger, 1995 [B53], the initial voltage distribution will be capacitive and slowly relaxes to a resistive distribution with the time constant of typical XLPE insulation (permittivity 0 r ε ε times volume resistivity ρ ). 2.3 8.85 10 12 1014 Ω m=2035 s F m × × − ×  .
As a result, in a hypothetical case of pure HVDC stress (constant voltage level only), the time constant needed for this transition would be over 33 min. As the duration of the charging phase of DAC is significant below this time with the test voltage levels as mentioned in Table A.1 and Table A.2 (See Annex A), the E-fields will stay below critical values [B13], [B80], not only for one DAC excitation but also for several excitations as typically applied during a DAC withstand test. The result is to produce only ac field stresses in the cable. To avoid the side effects of a unipolar excitation time and possible space charge development, it is recommended to stay with an excitation time of less than 100 s. If this value cannot be met, the charging supply current has to be increased to reduce the charging time. Alternatively a bipolar charging procedure (charging with positive and negative voltage) with a suitable HV source can be used. IEEE Std 400.4 pdf download.