IEEE 1838-2019 pdf free download – IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits.
1.1 Scope IEEE Std 1838™-2019 standardizes mandatory and optional on-chip hardware components for 3D test access. It is intended that in the future a standard is developed for a formal, computer-readable language in which implementation choices for the three-dimensional design-for-test (3D-DfT) hardware can be specifed and described. An idea of a language/data structure has been described in [B5]. 1
The aim of IEEE Std 1838 is to defne at die-level standardized and scalable 3D-DfT features based on and working with digital scan-based test access, such that when compliant dies are stacked, a stack-level 3D-DfT test access architecture emerges with a minimum functionality and many optional extensions. IEEE Std 1838 provides a modular test access architecture, in which dies and interconnect layers between adjacent stacked dies can be tested individually. The focus of the standard is testing the intra-die circuitry as well as the inter- die interconnects in pre-bond, mid-bond, and post-bond cases in pre-packaging, post-packaging, and board- level situations.
The standard provides test access via a mandatory one-bit (‘serial’) input/output test port and optional multi-bit (‘parallel’) test ports. The standard is die-centric, i.e., compliance to the standard pertains to a die (and not to a stack of dies). Standardized die-level design-for-test (DfT) features comprise a stack-level test access architecture. In this way, the standard enables interoperability between die makers and stack maker. The standard does not address stack-level challenges and solutions. The most prominent example of this is that the standard does not address compliance of the stack to IEEE Std 1149.1™ boundary scan for board-level interconnect testing (although the standard certainly does not prohibit application thereof). 2
IEEE Std 1838 does not mandate specifc defect or fault models, specifc test generation methods, nor specifc die-internal 2D-DfT features. However, the standard leverages existing 2D-DfT wherever applicable and appropriate, including test access ports (such as specifed in IEEE Std 1149.1), on-chip DfT such as internal scan chains and wrappers of embedded cores (such as specifed in IEEE Std 1500™), and on-chip design-for- debug and embedded instruments (such described in IEEE Std 1687™).
Stacking of dies requires that the vertical interconnects [e.g., micro-bumps and through-silicon vias (TSVs)] are aligned with respect to footprint (i.e., matching x,y layout locations), mechanical properties (i.e.,matching materials, diameter, height, etc.), and electrical properties (i.e., matching driver/receiver pairs). As a generic DfT-only standard, IEEE Std 1838 does not govern these items. Similar to IEEE Std 1149.1 and IEEE Std 1500, it only defnes a DfT architecture:
— Number, name, type, and function of test I/Os
— On-chip DfT hardware and corresponding description
— Clock-cycle accurate test operation protocol
Consequently, off-the-shelf IEEE Std 1838-compliant dies are not guaranteed to ‘plug-n-play’ with each other without further physical alignment. The additional test I/Os as defned by IEEE Std 1838 require more parameters: footprint, mechanical, and electrical properties (but the same is true for the functional interfaces).
1.2 Three-dimensional integrated circuits (ICs) stacking technology
The market continues to pull for integrated circuits (ICs) with higher performance, better energy-effciency, and lower cost. While conventional transistor scaling runs into increasing technical and fnancial hurdles, the baton in the race to create attractive new IC products that meet market expectations is gradually being taken over by innovations in multi-die stack-assembly and packaging techniques. Large-array fne-pitch micro-bumps implement dense high-performance low-power inter-die interconnects. Through-silicon vias in combination with wafer thinning provide electrical connections via the back-side of a die’s substrate, enabling stacks of more than two dies. Interposer dies, possibly implemented in a passive technology, offer low-cost high-performance ways to interconnect multiple dies. Packaging costs can be drastically reduced by using cheaper materials and processes and by turning packaging into a wafer-level operation. The I/O-to-pin fan-out functionality of package substrates can be replaced by redistribution metal layers, cost-effectively manufactured at wafer level. And the cost of plastic or ceramic packages can be circumvented by applying epoxy mold compounds at wafer level.IEEE 1838 pdf download.