IEEE 1149.10-2017 pdf free download – IEEE Standard for High-Speed Test Access Port and On-Chip Distribution Architecture.
This standard defines a high speed test access port for delivery of test data, a packet format for describing the test payload, and a distribution architecture for converting the test data to/from on-chip test structures. The standard re-uses existing high speed I/O (HSIO) known in the industry for the high speed test access port (HSTAP). The HSIO connects to an on-chip distribution architecture through a common interface. The scope includes the distribution architecture test logic and packet decoder logic. The objective of the distribution architecture and packet decoder is that it can be readily re-used with different integrated circuits (ICs) that host different HSIO technology, such that the standard addresses as large a part of the industry as possible. The scope includes IEEE 1149.1 Boundary-Scan Description Language (BSDL) and Procedural Description Language (PDL) documentation, which can be used for configuring a mission mode HSIO to a test mode compatible with the HSTAP. The same BSDL and PDL can then be used to deliver high-speed data to the on-chip test structures.
1.2 Need Test time has always been an important metric for system on a chip (SoC).
The original IEEE 1149.1 test access port is fine for simple board interconnect tests, but as on-chip operations via the IEEE 1149.1 test access port (TAP) have increased, the use of the IEEE 1149.1 TAP becomes inefficient for board test and on-board field programmable gate array (FPGA) configuration. Large FPGAs take tens of minutes to configure through the IEEE 1149.1 TAP. The IEEE 1149.1 TAP has always been too slow for production SoC test. Wide test access mechanisms (TAMs) are used to increase test throughput during production IC test at the cost of requiring more tester resources. Wide TAMs are also not useful for test re-use at the board/system level because many of the I/O of the TAM are not accessible. Pin limitations also exist where the pins required for the IEEE 1149.1 TAP cannot be supported by a small package or die. A high-speed test access port and packet encoder/decoder and distribution architecture (PEDDA) is needed by the industry to standardize a faster test data delivery mechanism for IC automatic test equipment (ATE), but also be re-usable at board and system level test. Today, in 2017, to get 10 Gbit/s data transfer on a die requires one hundred touch-downs for sending data in at 100 Mbit/s and one hundred touch-downs for receiving data at 100 Mbit/s with one hundred scan chains that meet the timing for a 100 MHz clock rate. IEEE Std 1149.10-2017™ offers an alternative to deliver the same test data bandwidth with just a differential receiver and transmitter: four pins, a system clock, and power.
By making the scan-channels “virtual,” tradeoffs can be made during design for test regarding scan rates, number of concurrent active scan channels, and the amount of test bandwidth desired. Mission mode pins exist for SERDES, serial parallel interface (SPI), I 2 C (I2C), and double data rate (DDR), which can be re-allocated for test purposes saving on dedicated test pins needed in the SoC to support IEEE 1149.1. IEEE Std 1149.10-2017 introduces the re-use of mission mode pins to facilitate either high-bandwidth test or low resource based test via two new objects: the HSTAP and the PEDDA. The HSTAP can layer on top of the mission mode pins (e.g., re-use the pins of SERDES, SPI, I2C, etc.) and deliver data to the PEDDA, which can access on-chip scan channels (test data registers and wrapper serial ports) to communicate data for test, debug, or FPGA configuration.IEEE 1149.10 pdf downkload.