IEC 63287-1-2021 pdf free download – Semiconductor devices – Generic semiconductor qualification guidelines – Part 1: Guidelines for IC reliability qualification.
5 Failure
5.1 Failure distribution Failure distribution of ICs can be broadly divided into three regions: early failure portion (e.g., t ELF = 1 year), random failure portion, and wear-out failure portion. Figure 1 shows the relationship between the field use time and the instantaneous failure rate (bathtub curve). Failure distributions for each region are described in detail in 5.2 to 5.4. Most early failures are screened within manufacturing processes of IC vendors. However, ICs not fully screened can expose problems in a relatively short period after their operation starts in the field.
Random failure has been considered to achieve a certain failure rate with respect to time, but actually, it is appropriate to consider as an extension of the early failure region where the failure rate continues to decline. Potentially induced failures outside of the supplier’s control, such as ESD, EOS and soft errors, should not be included in the failure rate calculations unless a total fail rate that includes these types of fail modes is intended. Wear-out failure is a failure which occurs due to the end of life of IC components such as transistors and interconnections, and indicates the life of the ICs themselves. Wear-out failure is a failure which depends on the usage load profile (time windows may be different). The number of failures increases with time, and every IC will eventually cause a failure beyond the intended design life of the part.
Wear-out failures are not considered in the same manner, because they have a totally different mechanism and therefore also a different mathematical description (failure distribution). Therefore, it is important to prevent this failure during the durable period. For ICs, the time to reach the cumulative failure probability of 0,1 5 over the design life of the part in the given application is generally defined as their design lifetime.
5.2 Early failure
5.2.1 Description
Since ICs contain very small feature sizes and are dense and complex, they are susceptible to defects generated in manufacturing processes. For this reason, good devices which satisfy required characteristics and functions are sorted out at the final stage of manufacturing processes. The ratio of good devices to the total amount produced and tested in this process is called yield. When sorting good devices, they are measured for as many items as possible including characteristics and functions required. However, some of these sorted good devices can include those with built-in latent defects or weaknesses which does not influence electrical characteristics, and they operate properly during sorting. When the yield is high, devices with these potential defects are less likely to be included. In contrast, when the yield is relatively low, there is a high possibility of mixture of these latent defect devices with good ones. Devices with these potential defects can eventually fail during use due to the shortened lifetime or the intensity of the user application.
A small amount of tested good devices which contain such defects is included in the manufacturing lot and, as such, its failure rate decreases with time. This is because non- defective ICs which are unlikely to cause a failure remain when defective ICs are removed after they cause a failure. In such a case, the shape parameter of the Weibull distribution: m is less than 1 (m < 1 ).IEC 63287-1 pdf download