IEC 60749-41-2020 pdf free download – Semiconductor devices – Mechanical and climatic test methods – Part 41: Standard reliability testing methods of non-volatile memory devices.
This part of lEC 60749 specifies the procedural requirements for performing valid endurance,retention and cross-temperature tests based on a qualification specification. Endurance andretention qualification specifications (for cycle counts,durations，temperatures,and samplesizes) are specified in JESD47 or are developed using knowledge-based methods such as inJEsD94.
Normative references
The following documents are referred to in the text in such a way that some or all of theircontent constitutes requirements of this document. For dated references, only the editioncited applies.For undated references, the latest edition of the referenced document (includingany amendments) applies.
IEC 60749-6,Semiconductor devices – Mechanical and climatic test methods – Part 6:Storage at high temperature
IEC 60749-23,Semiconductor devices – Mechanical and climatic test methods – Part 23: Hightemperature operating life
JESD47,Stress-Test-Driven Qualification of Integrated Circuits
JESD94,Application Specific Qualification Using Knowledge Based Test Methodology
3Terms and definitions
For the purposes of this document, the following terms and definitions apply.
IsO and lEC maintain terminological databases for use in standardization at the followingaddresses:
IEC Electropedia: available at http://www.electropedia.orgl
Iso Online browsing platform: available at http://www.iso.orglobp
3.1
cross-temperature test CTT
data read verification across the opposite end of the operating temperature range such thatwhen programming occurs at low temperature it is properly read at hot temperature or viceversa
Note 1 to entry: This note applies to the French language only.
3.2
cross-temperature test failureCTTF
data read verification failure across the opposite end of the operating temperature rangewhere it was programmed
Note 1 to entry: This note applies to the French language only.3.3
electrically erasable programmable read-only memoryEEPROM
reprogrammable read-only memory in which the cells at each address can be erasedelectrically and reprogrammed electrically
Note 1 to entry: The term EEPROM in this document includes all such memories,including flash EEPROMintegrated circuits and embedded memory in integrated circuits such as Erasable Programmable Logic Devices(EPLDs) and microcontrollers. Destructive-read memories such as ferroelectric memories，in which the readoperation re-writes the data in the memory cells, are beyond the scope of this document.
Note 2 to entry: This note applies to the French language only.
3.4
data pattern
mix of several 1s and 0s in the memory and their physical or logical positions
Note 1 to entry: A device can be single-bit-per-cell (SBC), meaning that one physical memory cell stores a “0” ora “1”, or multiple-bits-per-cell (MBC), meaning that one cell stores typically two bits of data: “o” . “01”,”10″, or “11”.in some MBC memories, the two bits represent logically-adjacent bit-pairs in each byte of data.For example,for2 bits per cell, a byte containing binary data 10110001 would correspond to four physical cells with data 2301 inbase-four logic. In other MBC memories, the two bits can represent bits in entirely different address locations. Foran SBC memory a physical checkerboard pattern consists of alternating 0s and 1s, with each 0 surrounded by 1son either side and above and below; a logical checkerboard pattern consists of data bytes AAH or 55H in whicheach 0 is logically adjacent to 1s. In some qualifications only logical positions are known.
3.5
endurance
ability of a reprogrammable read-only memory to withstand data rewrites and still comply withapplicable specifications
Note 1 to entry: EEPROM device specifications often require an erase step before reprogramming data; in thiscase a data rewrite includes both erase and programming steps, which together are called a program/erase cycle.Direct-write memories allow data to be written directly over old, without an erase; in this case the use of thegeneric term “programlerase cycle”will refer to a single rewrite with no erase. For single-bit-per-cell(SBC)memories that require an erase step, one program/erase cycle consists of programming cells (typically to “0”) andthen erasing (“1”).For the comparable multiple-bits-per-cell (MBC) case, a cycle would consist of programmingcells (to “o”.*”i”,or “2” for two bits per cell) and then erasing (“3” for two bits per cell).IEC 60749-41 pdf download.