IEEE 1450.6.1-2009 pdf free download – IEEE Standard for Describing On-Chip Scan Compression.
7. Semantics updates
This clause details any semantics that were extended or changed (no syntax changes).
a) All Loops defined in MacroDef or Procedure statements for on-chip scan compression logic imply a full load/unload sequence.
b) Mapping symbolic signal names to design netlist names (anchor points) are mandatory for each ScanIn and ScanOut of each ScanStructures block that defines an internal scan chain. Scan chains used by test logic do not need this mapping. When a scanin/scanout of a ScanStructures block matches a design netlist pin path name, no anchor point is needed. All inversions that occur on the ScanStructures side of the anchor point shall be included in the ScanStructures definition and those on the CompressionStructures side in the CompressionStructures definition. Anchor points (see Figure 3) can be defined on any port of any netlist gate and are specified by using the ScanCells and Signals NameMaps defined in 18.3 of IEEE Std 1450.1-2005. Setting anchor points on state elements can be useful, since these names do not change as much as logic gates do during design. When anchor points are defined using NameMaps for ScanStructures defined inside a CoreType block, the ScanIn and ScanOut name being mapped shall be scoped using the core instance name followed by a colon (: ). When a CoreType block uses design netlist pin path names to identify internal core anchor points to the level of design hierarchy of the CoreType block, the CoreInstance CORE _ TYPE _ NAME can be mapped to a design netlist instance name using NameMaps. If no NameMap assignment exists for the CORE _ TYPE _ NAME or the SI/SO ports in the internal core chains, the CORE _ TYPE _ NAME defaults to the design netlist instance name. In the case where the SI/SO ports in the internal core chains are not mapped (using NameMaps), the core anchor points shall be mapped using the CoreInstance design netlist instance name (the default) or the mapped name (if mapped via NameMaps), plus a hierarchical delimiter and the core anchor point design netlist pin path name.
c) All on-chip scan compression logic shall be fully specified from anchor points to input and output signal pins through State, logic_expression, or MacroDef or Procedure statements.
d) Core non-pseudo ScanIn and ScanOut signal pins cannot be daisy-chained with other scan chains during core integration when on-chip scan compression logic is defined using those pins.
e) Any core with on-chip scan compression logic shall have fully specified patterns; it shall not rely on padding assumptions from the Signal block.
f) When Pseudo signals are specified in the MacroDef and Procedure blocks with no waveform, it is assumed to not be pulsed and to change at time 0. If a pulse is needed on a Pseudo signal, a Waveforms specification is required. g) When test logic insertion uses a different tool than pattern generation and a MacroDef or Procedure has a Control, Observe, or ControlObserve Purpose assigned in the PatternInformation portion of the Environment block, that Procedure or MacroDef shall not be modified by the pattern generation tool.IEEE 1450.6.1 pdf download.
IEEE 1450.6.1-2009 pdf free download – IEEE Standard for Describing On-Chip Scan Compression
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